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A RISC microprocessor descended from theBerkley RISC design. Like the SPARC design that wasintroduced shortly afterward, the 29000 has a large registerset split into local and global sets. But though it wasintroduced before the SPARC, it has a more elegant method ofregister management.The 29000 has 64 global registers, in comparison to theSPARC's eight. In addition, the 29000 allows variable sizedwindows allocated from the 128 register stack cache. Thecurrent window or stack frame is indicated by a stack pointer,a pointer to the caller's frame is stored in the currentframe, like in an ordinary stack (directly supporting stacklanguages like C, a CISC-like philosophy). Spills andfills occur only at the ends of the cache, and registers aresaved/loaded from the memory stack. This allows variablewindow sizes, from 1 to 128 registers. This flexibility, plusthe large set of global registers, makes register allocationeasier than in SPARC.There is no special condition code register - any generalregister is used instead, allowing several condition codes tobe retained, though this sometimes makes code more complex.An instruction prefetch buffer (using burst mode) ensuresa steady instruction stream. To reduce delays caused by abranch to another stream, the first four new instructions arecached and next time a cached branch (up to sixteen) is taken,the cache supplies instructions during the initial memoryaccess delay.Registers aren't saved during interrupts, allowing theinterrupt routine to determine whether the overhead isworthwhile. In addition, a form of register access control isprovided. All registers can be protected, in blocks of 4,from access. These features make the 29000 useful forembedded applications, which is where most of these processorsare used, allowing it the claim to be "the most popular RISCprocessor". The 29000 also includes an MMU and support forthe AMD 29027 FPU.