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A data-driven circuit design technique where,instead of the components sharing a common clock andexchanging data on clock edges, data is passed on as soon asit is available. This removes the need to distribute a commonclock signal throughout the circuit with acceptable clockskew. It also helps to reduce power dissipation in CMOScircuits because gates only switch when they are doinguseful work rather than on every clock edge.There are many kinds of asynchronous logic. Data signals mayuse either "dual rail encoding" or "data bundling". Each dualrail encoded Boolean is implemented as two wires. Thisallows the value and the timing information to be communicatedfor each data bit. Bundled data has one wire for each databit and another for timing. Level sensitive circuitstypically represent a logic one by a high voltage and a logiczero by a low voltage whereas transition signalling uses achange in the signal level to convey information. A speedindependent design is tolerant to variations in gate speedsbut not to propagation delays in wires; a delay insensitivecircuit is tolerant to variations in wire delays as well.The purest form of circuit is delay-insensitive and usesdual-rail encoding with transition signalling. A transitionon one wire indicates the arrival of a zero, a transition onthe other the arrival of a one. The levels on the wires areof no significance. Such an approach enables the design offully delay-insensitive circuits and automatic layout as thedelays introduced by the layout compiler can't affect thefunctionality (only the performance). Level sensitive designscan use simpler, stateless logic gates but require a "returnto zero" phase in each transition. (http://cs.man.ac.uk/amulet/async/).