Definitions of dynamic random-access memory

  1. ( DRAM) A type of semiconductor memory in which theinformation is stored in capacitors on a MOS integratedcircuit. Typically each bit is stored as an amount ofelectrical charge in a storage cell consisting of a capacitorand a transistor. Due to leakage the capacitor dischargesgradually and the memory cell loses the information.Therefore, to preserve the information, the memory has to berefreshed periodically. Despite this inconvenience, the DRAMis a very popular memory technology because of its highdensity and consequent low price.The first commercially available DRAM chip was the Intel1103, introduced in 1970.Early DRAM chips, containing up to a 16k x 1 ( 16384 locationsof one bit each), needed 3 supply voltages (+ 5V, - 5V and+12V). Beginning with the 64 kilobit chips, charge pumpswere included on-chip to create the necessary supply voltagesout of a single + 5V supply. This was necessary to fit thedevice into a 16-pin DIL package, which was the preferredpackage at the time, and also made them easier to use.To reduce the pin count, thereby helping miniaturisation,DRAMs generally had a single data line which meant that acomputer with an N bit wide data bus needed a " bank" of ( atleast) N DRAM chips. In a bank, the address and controlsignals of all chips were common and the data line of eachchip was connected to one of the data bus lines.Beginning with the 256 kilobit DRAM, a tendency towardsurface mount packaging arose and DRAMs with more than onedata line appeared ( e.g. 64k x 4), reducing the number ofchips per bank. This trend has continued and DRAM chips withup to 36 data lines are available today. Furthermore,together with surface mount packages, memory manufacturersbegan to offer memory modules, where a bank of memory chipswas preassembled on a little printed circuit board ( SIP = Single Inline Pin Module, SIMM = Single Inline Memory Module,DIMM = Dual Inline Memory Module). Today, this is thepreferred way to buy memory for workstations and personalcomputers.DRAM bit cells are arranged on a chip in a grid of rows andcolumns where the number of rows and columns are usually apower of two. Often, but not always, the number of rows andcolumns is the same. A one megabit device would then have1024 x 1024 memory cells. A single memory cell can beselected by a 10-bit row address and a 10-bit column address.To access a memory cell, one entire row of cells is selectedand its contents are transferred into an on-chip buffer. Thisdischarges the storage capacitors in the bit cells. Thedesired bits are then read or written in the buffer. The(possibly altered) information is finally written back intothe selected row, thereby refreshing all bits ( recharging thecapacitors) in the row.To prevent data loss, all bit cells in the memory need to berefreshed periodically. This can be done by reading all rowsin regular intervals. Most DRAMs since 1970 have beenspecified such that one of the rows needs to be refreshed atleast every 15.625 microseconds. For a device with 1024 rows,a complete refresh of all rows would then take up to 16 ms; inother words, each cell is guaranteed to hold the data for 16ms without refresh. Devices with more rows have accordinglylonger retention times.Many varieties of DRAM exist today. They differ in the waythey are interfaced to the system - the structure of thememory cell itself is essentially the same." Traditional" DRAMs have multiplexed address lines andseparate data inputs and outputs. There are three controlsignals: RAS\ ( row address strobe), CAS\ ( column addressstrobe), and WE\ ( write enable) ( the backslash indicates anactive low signal). Memory access procedes as follows:1. The control signals initially all being inactive ( high), amemory cycle is started with the row address applied to theaddress inputs and a falling edge of RAS\ . This latches therow address and " opens" the row, transferring the data in therow to the buffer. The row address can then be removed fromthe address inputs since it is latched on-chip. 2. With RAS\still active, the column address is applied to the addresspins and CAS\ is made active as well. This selects thedesired bit or bits in the row which subsequently appear atthe data output(s). By additionally activating WE\ the dataapplied to the data inputs can be written into the selectedlocation in the buffer. 3. Deactivating CAS\ disables thedata input and output again. 4. Deactivating RAS\ causes thedata in the buffer to be written back into the memory array.Certain timing rules must be obeyed to guarantee reliableoperation. 1. RAS\ must remain inactivate for a while beforethe next memory cycle is started to provide sufficient timefor the storage capacitors to charge ( Precharge Time). 2. Ittakes some time from the falling edge of the RAS\ or CAS\signals until the data appears at the data output. This isspecified as the Row Access Time and the Column Access Time.Current DRAM's have Row Access Times of 50-100 ns and ColumnAccess Times of 15-40 ns. Speed grades usually refer to theformer, more important figure.Note that the Memory Cycle Time, which is the minimum timefrom the beginning of one access to the beginning of the next,is longer than the Row Access Time ( because of the PrechargeTime). Multiplexing the address pins saves pins on the chip, butusually requires additional logic in the system to properlygenerate the address and control signals, not to mentionfurther logic for refresh. Therefore, DRAM chips are usuallypreferred when ( because of the required memory size) theadditional cost for the control logic is outweighed by thelower price.Based on these principles, chip designers have developed manyvarieties to improve performance or ease system integration ofDRAMs:PSRAMs ( Pseudo Static Random Access Memory) are essentiallyDRAMs with a built-in address multiplexor and refreshcontroller. This saves some system logic and makes the devicelook like a normal SRAM. This has been popular as a lowercost alternative for SRAM in embedded systems. It is not acomplete SRAM substitute because it is sometimes busy whendoing self-refresh, which can be tedious.Nibble Mode DRAM can supply four successive bits on one dataline by clocking the CAS\ line.Page Mode DRAM is a standard DRAM where any number ofaccesses to the currently open row can be made while the RASsignal is kept active.Static Column DRAM is similar to Page Mode DRAM, but to accessdifferent bits in the open row, only the column address needsto be changed while the CAS\ signal stays active. The rowbuffer essentially behaves like SRAM.Extended Data Out DRAM ( EDO DRAM) can continue to outputdata from one address while setting up a new address, for usein pipelined systems.DRAM used for Video RAM ( VRAM) has an additional longshift register that can be loaded from the row buffer. Theshift register can be regarded as a second interface to thememory that can be operated in parallel to the normalinterface. This is especially useful in frame buffers forCRT displays. These frame buffers generate a serial datastream that is sent to the CRT to modulate the electron beam.By using the shift register in the VRAM to generate thisstream, the memory is available to the computer through thenormal interface most of the time for updating the displaydata, thereby speeding up display data manipulations.SDRAM ( Synchronous DRAM) adds a separate clock signal to thecontrol signals. It allows more complex state machines onthe chip and high speed " burst" accesses that clock a seriesof successive bits out ( similar to the nibble mode). CDRAM ( Cached DRAM) adds a separate static RAM array used forcaching. It essentially combines main memory and cachememory in a single chip. The cache memory controller needs tobe added externally.RDRAM ( Rambus DRAM) changes the system interface of DRAMcompletely. A byte-wide bus is used for address, data andcommand transfers. The bus operates at very high speed: 500million transfers per second. The chip operates synchronouslywith a 250MHz clock. Data is transferred at both rising andfalling edges of the clock. A system with signals at suchfrequencies must be very carefully designed, and the signalson the Rambus Channel use nonstandard signal levels, making itincompatible with standard system logic. These disadvantagesare compensated by a very fast data transfer, especially forburst accesses to a block of successive locations.A number of different refresh modes can be included in some ofthe above device varieties:RAS\ only refresh: a row is refreshed by an ordinary readaccess without asserting CAS\. The data output remainsdisabled.CAS\ before RAS\ refresh: the device has a built-in counterfor the refresh row address. By activating CAS\ beforeactivating RAS\, this counter is selected to supply the rowaddress instead of the address inputs.Self-Refresh: The device is able to generate refresh cyclesinternally. No external control signal transitions other thanthose for bringing the device into self-refresh mode areneeded to maintain data integrity.
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