\ɐdɹˈɛsɪŋ mˈə͡ʊd], \ɐdɹˈɛsɪŋ mˈəʊd], \ɐ_d_ɹ_ˈɛ_s_ɪ_ŋ m_ˈəʊ_d]\
Definitions of ADDRESSING MODE
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1. One of a set of methods forspecifying the operand(s) for a machine code instruction.Different processors vary greatly in the number of addressingmodes they provide. The more complex modes described belowcan usually be replaced with a short sequence of instructionsusing only simpler modes.The most common modes are "register" - the operand is storedin a specified register; "absolute" - the operand is storedat a specified memory address; and "immediate" - the operandis contained within the instruction.Most processors also have indirect addressing modes, e.g."register indirect", "memory indirect" where the specifiedregister or memory location does not contain the operand butcontains its address, known as the "effective address". Foran absolute addressing mode, the effective address iscontained within the instruction.Indirect addressing modes often have options for pre- or post-increment or decrement, meaning that the register or memorylocation containing the effective address is incremented ordecremented by some amount (either fixed or also specified inthe instruction), either before or after the instruction isexecuted. These are very useful for stacks and foraccessing blocks of data. Other variations form the effectiveaddress by adding together one or more registers and one ormore constants which may themselves be direct or indirect.Such complex addressing modes are designed to support accessto multidimensional arrays and arrays of data structures.The addressing mode may be "implicit" - the location of theoperand is obvious from the particular instruction. Thiswould be the case for an instruction that modified aparticular control register in the CPU or, in a stack basedprocessor where operands are always on the top of the stack.2. In IBM System 370/XA the addressing mode bit controlsthe size of the effective address generated. When this bitis zero, the CPU is in the 24-bit addressing mode, and 24 bitinstruction and operand effective addresses are generated.When this bit is one, the CPU is in the 31-bit addressingmode, and 31-bit instruction and operand effective addressesare generated.["IBM System/370 Extended Architecture Principles ofOperation", Chapter 5., 'Address Generation', BiModalAddressing].
By Denis Howe